本文基于Altera的FPGA（StatixⅡ-EP2S30F484C3）架構(gòu)，實(shí)現(xiàn)了碼率為1/2，幀長(zhǎng)為1008bits的規(guī)則（3,6）LDPC碼譯碼器。所采用的最小-和算法相對(duì)于傳統(tǒng)的和-積算法在不損失譯碼性能的前提下，降低了硬件實(shí)現(xiàn)的復(fù)雜度，設(shè)計(jì)的并行結(jié)構(gòu)有效地解決了串行結(jié)構(gòu)所帶來譯碼延時(shí)過大的問題，最大譯碼速率可達(dá)到60Mbit/s。為L(zhǎng)DPC碼的實(shí)際應(yīng)用奠定了良好的基礎(chǔ)。
關(guān)鍵詞：LDPC碼；校驗(yàn)矩陣；最小和算法；FPGA

Design and Implementation of Parallel Architectures Decoder for（3,6）LDPC Codes Based on FPGA ZHONG Yong-xin， DU Xing-min （The Engineering Institute,Air Force Engineering University,Xi’an 710038,China） Abstract：In this paper,a decoder for (3,6) regular LDPC codes with code rate of 1/2 and block length of 1008 bits has been implemented based on FPGA(StatixⅡ-EP2S30F484C3) of Altera. In compare with traditional sum-product algorithm,min-sum algorithm has close performance and reduces the complication of hardware.Parallel architectures solves the problem of long time delay in serial architectures effectively and can achieve a decoding rate of 50Mbps.It lays a good foundation for application of LDPC codes.
Key words：LDPC codes；Parity check matrix；Min-sum algorithm；FPGA