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FMC-Imageon Xilinx ML605參考設(shè)計

2079476 2021-05-22 | pdf | 355.73KB | 次下載 | 2積分

資料介紹

This version (19 Nov 2019 15:00) was approved by Stanca-Florina Pop.The Previously approved version (18 Nov 2019 15:59) is available.

FMC-IMAGEON Xilinx Reference Design

FMC-IMAGEON Xilinx Reference Design

Introduction

The FMC-IMAGEON is a HDMI input/output FMC card that provides high definition video interface for Xilinx FPGAs. The HDMI input interface is implemented with the ADV7611, a 165MHz, 24bit pixel output, HDCP capable HDMI 1.4a receiver. The HDMI output interface is implemented with the ADV7511, a 225MHz, 36bit deep color, HDMI 1.4 transmitter. This reference design provides the video and audio interface between the FPGA and ADV7511/ADV7611 on board. The video uses a 16bit 422 YCbCr interface and the audio uses a single bit SPDIF interface in both directions.

Supported Devices

FMC-IMAGEON

Supported Carriers

ZedBoard

Required Hardware

One of the supported carrier and FMC-IMAGEON boards.
HDMI Monitor (should be capable of supporting 1080p and/or 720p for the demo files).

Required Software

We upgrade the Xilinx tools on every release. The supported version number can be found in our git repository .
A UART terminal (Tera Term/Hyperterminal), Baud rate 57600.

Using the reference design

Functional description

Xilinx block diagram

-[-/iframe> </p> </div> <h4 id="fmc-imageon_block_diagram">FMC-IMAGEON block diagram</h4> <div id="ouusgtyctptl" class="level4"> <p> <iframe src="/_media/resources/fpga/xilinx/fmc/fmc-imageon/imageon_fmc_1.svg?w=600&h=504&tok=233871" width="600" height="504" class="svgpureinsert media" frameborder="0" title="HDL Block Diagram">

The reference design consists of two independent IP modules.

The video part consists of an AXI DMAC interface and the ADV7511/ADV7611 video interface. The video interface consists of a 16bit YCbCr 422 with embedded synchronization signals.

Video Transmit (DMA to HDMI)

In the transmit direction, the DMA streams frame data to this core. The internal buffers of this IP are small (1k) and do NOT buffer any frames as such. Additional resources may cause loss of synchronization due to DDR bandwidth requirements. The video core is capable of supporting any formats through a set of parameter registers (given below). The pixel clock is generated internal to the device and must be configured for the correct pixel frequency. It also allows a programmable color pattern for debug purposes. A zero to one transition on the enable bits trigger the corresponding action for HDMI enable and color pattern enable.

The reference design defaults to the 1080p video mode. Users may change the video settings by programming the video size registers. The core requires a corresponding pixel clock to generate the video. This clock must be generated externally.

Note that the pixel frequency for 1080p is 148.5MHz.

The reference design reads 24bits of RGB data from DDR and performs color space conversion (RGB to YCbCr) and down sampling (444 to 422). If bypassed, the lower 16bits of DDR data is passed to the HDMI interface as it is.

A color pattern register provides a quick check of any RGB values on the monitor. If enabled, the register data is used as the pixel data for the entire frame.

Video Receive (HDMI to DMA)

In the receive direction, the HDMI data is first decoded and the synchronization signals are generated. The core then streams video data to DMA. The internal buffers of this IP are small (1k) and do NOT buffer any frames as such. Additional resources may cause loss of synchronization due to DDR bandwidth requirements. The video core is capable of supporting any formats through a set of parameter registers (given below). The core runs at the pixel clock from ADV7611.

The core decodes the active video size from the received data and compares it against an expected video size. If they do not match, the core will NOT stream data to DMA to avoid possible lock up conditions in the DMA core due to byte length mismatches. Also, the reference design performs color space conversion (YCbCr to RGB) and up sampling (422 to 444). If bypassed, the lower 16bits of DDR data is passed to the DMA interface as it is.

Test pattern generators and monitors are provided at each interface and clock domain boundaries. The default configuration is in loop back mode with the HDMI interface acting as a direct pass through.

Audio

The audio part consists of an AXI DMAC interface and the ADV7511 spdif audio interface. The audio clock is derived from the bus clock. A programmable register (see below) controls the division factor. The audio data is read from the DDR as two 16bit words for the left and right channels. It is then transmitted on the SPDIF frame. The sample frequency and format may be controlled using the registers below. The reference design defaults to 48KHz.

Registers

Base (common to all cores)

0x0000	0x0000	REG_VERSION				Version and Scratch Registers
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[31:0]	VERSION[31:0]	RO	0x00000000	Version number. Unique to all cores.
0x0001	0x0004	REG_ID				Version and Scratch Registers
		[31:0]	ID[31:0]	RO	0x00000000	Instance identifier number.
0x0002	0x0008	REG_SCRATCH				Version and Scratch Registers
		[31:0]	SCRATCH[31:0]	RW	0x00000000	Scratch register.
0x0003	0x000c	REG_CONFIG				Version and Scratch Registers
		[0]	IQCORRECTION_DISABLE	RO	0x0	If set, indicates that the IQ Correction module was not implemented. (as a result of a configuration of the IP instance)
		[1]	DCFILTER_DISABLE	RO	0x0	If set, indicates that the DC Filter module was not implemented. (as a result of a configuration of the IP instance)
		[2]	DATAFORMAT_DISABLE	RO	0x0	If set, indicates that the Data Format module was not implemented. (as a result of a configuration of the IP instance)
		[3]	USERPORTS_DISABLE	RO	0x0	If set, indicates that the logic related to the User Data Format (e.g. decimation) was not implemented. (as a result of a configuration of the IP instance)
		[4]	MODE_1R1T	RO	0x0	If set, indicates that the core was implemented in 1 channel mode. (e.g. refer to AD9361 data sheet)
		[5]	DELAY_CONTROL_DISABLE	RO	0x0	If set, indicates that the delay control is disabled for this IP. (as a result of a configuration of the IP instance)
		[6]	DDS_DISABLE	RO	0x0	If set, indicates that the DDS is disabled for this IP. (as a result of a configuration of the IP instance)
		[7]	CMOS_OR_LVDS_N	RO	0x0	CMOS or LVDS mode is used for the interface. (as a result of a configuration of the IP instance)
		[8]	PPS_RECEIVER_ENABLE	RO	0x0	If set, indicates the PPS receiver is enabled. (as a result of a configuration of the IP instance)
		[9]	SCALECORRECTION_ONLY	RO	0x0	If set, indicates that the IQ Correction module implements only scale correction. IQ correction must be enabled. (as a result of a configuration of the IP instance)
0x0004	0x0010	REG_PPS_IRQ_MASK				PPS Interrupt mask
		[0]	PPS_IRQ_MASK	RW	0x1	Mask bit for the 1PPS receiver interrupt
0x0007	0x001c	REG_FPGA_INFO				FPGA device information Intel encoded values Xilinx encoded values
		[31:24]	FPGA_TECHNOLOGY	RO	0x0	Encoded value describing the technology/generation of the FPGA device (arria 10/7series)
		[23:16]	FPGA_FAMILY	RO	0x0	Encoded value describing the family variant of the FPGA device(e.g., SX, GX, GT or zynq, kintex, virtex)
		[15:8]	SPEED_GRADE	RO	0x0	Encoded value describing the FPGA's speed-grade
		[7:0]	DEV_PACKAGE	RO	0x0	Encoded value describing the device package. The package might affect high-speed interfaces
Wed Feb 10 15:54:55 2021

HDMI Transmit (axi_hdmi_tx)

Click to expand regmap

0x0010	0x0040	REG_RSTN				HDMI Interface Control & Status
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[0]	RSTN	RW	0x0	Reset, a common reset is used for all the interface modules, The default is reset (0x0), software must write 0x1 to bring up the core.
0x0011	0x0044	REG_CNTRL1				HDMI Interface Control & Status
		[2]	SS_BYPASS	RW	0x0	If set (0x1) bypasses the chroma sub-sampler. This is primarily intended to be used to send the test-pattern directly to the HDMI transmitter without modifying it.
		[1]	RESERVED	RO	0x0	Reserved
		[0]	CSC_BYPASS	RW	0x0	If set (0x1) bypasses color space conversion (if equipped). And depending on its value, the default value of color space boundaries is set in the REG_CLIPP_MAX and REG_CLIPP_MIN registers.
0x0012	0x0048	REG_CNTRL2				HDMI Interface Control & Status
		[1:0]	SOURCE_SEL	RW	0x0	Select the HDMI data source- register constant (0x3), incr-pattern (0x2), input (0x1) or disabled (0x0).
0x0013	0x004c	REG_CNTRL3				HDMI Interface Control & Status
		[23:0]	CONST_RGB[23:0]	RW	0x000000	This is the RGB value transmitted, if the source is constant (see above).
0x0015	0x0054	REG_CLK_FREQ				HDMI Interface Control & Status
		[31:0]	CLK_FREQ[31:0]	RO	0x00000000	Interface clock frequency. This is relative to the processor clock and in many cases is 100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be the same as the interface clock- software must consider device specific implementation parameters to calculate the final sampling clock.
0x0016	0x0058	REG_CLK_RATIO				HDMI Interface Control & Status
		[31:0]	CLK_RATIO[31:0]	RO	0x00000000	Interface clock ratio - as a factor actual received clock. This is implementation specific and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).
0x0017	0x005c	REG_STATUS				ADC Interface Control & Status
		[0]	STATUS	RO	0x0	Interface status, if set indicates no errors. If not set, there are errors, software may try resetting the cores.
0x0018	0x0060	REG_VDMA_STATUS				HDMI Interface Control & Status
		[1]	VDMA_OVF	RW1C	0x0	If set, indicates vdma overflow.
		[0]	VDMA_UNF	RW1C	0x0	If set, indicates vdma underflow.
0x0019	0x0064	REG_TPM_STATUS				HDMI Interface Control & Status
		[1]	HDMI_TPM_OOS	RW1C	0x0	If set, indicates TPM OOS at the HDMI interface.
		[0]	VDMA_TPM_OOS	RW1C	0x0	If set, indicates TPM OOS at the VDMA interface.
0x001a	0x0068	REG_CLIPP_MAX				HDMI Interface Control & Status
		[23:16]	R_MAX/Cr_MAX	RW	0xF0	Defines the maximum value for clipping the red or red-difference chroma component. Default value are 0xf0 for red-difference chroma and 0xfe for red.
		[16:8]	G_MAX/Y_MAX	RW	0xEB	Defines the maximum value for clipping the green or luma component. Default values are 0xeb for luma and and 0xfe for green.
		[7:0]	B_MAX/Cb_MAX	RW	0xF0	Defines the maximum value for clipping the blue or blue-difference chroma component. Default value are 0xf0 for blue-difference chroma and 0xfe for blue.
0x001b	0x006c	REG_CLIPP_MIN				HDMI Interface Control & Status
		[23:16]	R_MIN/Cr_MIN	RW	0x10	Defines the minimum value for clipping the red or red-difference chroma component. Default value are 0x10 for red-difference chroma and 0x01 for red.
		[16:8]	G_MIN/Y_MIN	RW	0x10	Defines the minimum value for clipping the green or luma component. Default values are 0x10 for luma and and 0x01 for green.
		[7:0]	B_MIN/Cb_MIN	RW	0x10	Defines the minimum value for clipping the blue or blue-difference chroma component. Default value are 0x10 for blue-difference chroma and 0x01 for blue.
0x0100	0x0400	REG_HSYNC_1				HDMI Interface Control & Status
		[31:16]	H_LINE_ACTIVE[15:0]	RW	0x0000	This is the horizontal line active pixel width (active resolution length). e.g. 1920 (1080p)
		[15:0]	H_LINE_WIDTH[15:0]	RW	0x0000	This is the horizontal line width (no. of pixel clocks per line). e.g. 2200 (1080p)
0x0101	0x0404	REG_HSYNC_2				HDMI Interface Control & Status
		[15:0]	H_SYNC_WIDTH[15:0]	RW	0x0000	This is the horizontal sync width (no. of pixel clocks). e.g. 44 (1080p)
0x0102	0x0408	REG_HSYNC_3				HDMI Interface Control & Status
		[31:16]	H_ENABLE_MAX[15:0]	RW	0x0000	This is the horizontal data enable maximum. It is the sum of H_ENABLE_MIN and the active pixel width. e.g. 2112 (192 + 1920) (1080p)
		[15:0]	H_ENABLE_MIN[15:0]	RW	0x0000	This is the horizontal data enable minimum. It is the sum of horizontal back porch (number of clock cycles between the falling edge of HSYNC to the rising edge of DE) and the sync width. e.g. 192 (44 + 148) (1080p)
0x0110	0x0440	REG_VSYNC_1				HDMI Interface Control & Status
		[31:16]	V_FRAME_ACTIVE[15:0]	RW	0x0000	This is the vertical frame active line width (active resolution height). e.g. 1080 (1080p)
		[15:0]	V_FRAME_WIDTH[15:0]	RW	0x0000	This is the vertical frame width (no. of lines per frame). e.g. 1125 (1080p)
0x0111	0x0444	REG_VSYNC_2				HDMI Interface Control & Status
		[15:0]	V_SYNC_WIDTH[15:0]	RW	0x0000	This is the vertical sync width (no. of lines). e.g. 5 (1080p)
0x0112	0x0448	REG_VSYNC_3				HDMI Interface Control & Status
		[31:16]	V_ENABLE_MAX[15:0]	RW	0x0000	This is the vertical data enable maximum. It is the sum of V_ENABLE_MIN and the active pixel height. e.g. 1121 (41 + 1080) (1080p)
		[15:0]	V_ENABLE_MIN[15:0]	RW	0x0000	This is the vertical data enable minimum. It is the sum of vertical back porch (number of lines between the falling edge of VSYNC to the rising edge of DE) and the sync width. e.g. 41 (36 + 5) (1080p)
Wed Feb 10 15:54:55 2021

HDMI Receive (axi_hdmi_rx)

Click to expand regmap

0x0010	0x0040	REG_RSTN				HDMI Interface Control & Status
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[0]	RSTN	RW	0x0	Reset, a common reset is used for all the interface modules, The default is reset (0x0), software must write 0x1 to bring up the core.
0x0011	0x0044	REG_CNTRL				HDMI Interface Control & Status
		[3]	EDGE_SEL	RW	0x0	If set (0x1), incoming data is registered on the falling edge of the clock first. The default uses rising edge.
		[2]	BGR	RW	0x0	If set (0x1), output BGR. The default is RGB.
		[1]	PACKED	RW	0x0	If set (0x1) pack 24bit RGB data on 32bit dwords. The default pads the MSB to zeros.
		[0]	CSC_BYPASS	RW	0x0	If set (0x1) bypasses color space conversion (if equipped).
0x0015	0x0054	REG_CLK_FREQ				HDMI Interface Control & Status
		[31:0]	CLK_FREQ[31:0]	RO	0x00000000	Interface clock frequency. This is relative to the processor clock and in many cases is 100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be the same as the interface clock- software must consider device specific implementation parameters to calculate the final sampling clock.
0x0016	0x0058	REG_CLK_RATIO				HDMI Interface Control & Status
		[31:0]	CLK_RATIO[31:0]	RO	0x00000000	Interface clock ratio - as a factor actual received clock. This is implementation specific and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).
0x0018	0x0060	REG_VDMA_STATUS				HDMI Interface Control & Status
		[1]	VDMA_OVF	RW1C	0x0	If set, indicates vdma overflow.
		[0]	VDMA_UNF	RW1C	0x0	If set, indicates vdma underflow.
0x0019	0x0064	REG_TPM_STATUS1				HDMI Interface Control & Status
		[1]	HDMI_TPM_OOS	RW1C	0x0	If set, indicates TPM OOS at the HDMI interface.
0x0020	0x0080	REG_TPM_STATUS2				HDMI Interface Control & Status
		[3]	VS_OOS	RW1C	0x0	If set, indicates VSYNC OOS - the core is unabled to detect/track VSYNC. Consecutive frames have different number of lines.
		[2]	HS_OOS	RW1C	0x0	If set, indicates HSYNC OOS - the core is unabled to detect/track HSYNC. Consecutive lines have different lengths.
		[1]	VS_MISMATCH	RW1C	0x0	If set, indicates received (detected) & programmed VSYNC (number of lines) mismatch. Incoming frames are stable but not the expected resolution.
		[0]	HS_MISMATCH	RW1C	0x0	If set, indicates received (detected) & programmed HSYNC (number of pixels) mismatch. Incoming frames are stable but not the expected resolution.
0x0100	0x0400	REG_HVCOUNTS1				HDMI Interface Control & Status
		[31:16]	VS_COUNT[15:0]	RW	0x0000	This is the expected active horizontal pixel lines (active resolution length). e.g. 1080 (1080p)
		[15:0]	HS_COUNT[15:0]	RW	0x0000	This is the expected horizontal pixel count (no. of pixel clocks per line). e.g. 1920 (1080p)
0x0101	0x0404	REG_HVCOUNTS2				HDMI Interface Control & Status
		[31:16]	VS_COUNT[15:0]	RO	0x0000	This is the detected horizontal active pixel lines (active resolution length). This field is valid only if VS_OOS is zero.
		[15:0]	HS_COUNT[15:0]	RO	0x0000	This is the detected horizontal pixel count (no. of pixel clocks per line). This field is valid only if HS_OOS is zero.
Wed Feb 10 15:54:55 2021

Audio Registers (axi_spdif_tx)

QW Address¹	Bits	Default	Name	Description
0x00	23:20	0	mode	Sample format 0 to 8 (0-16bit, 8-24bit).
	15:8	0	ratio	Clock divider for the transmit frequency = bus_clock/(1+ratio).
	1	0	txdata	Transmit data buffer enable (0x1) or disable (0x0).
	0	0	txenable	Transmitter enable (0x1) or disable (0x0).
0x01	7:6	0	frequency	Sample frequency 0(44.1KHz), 1(48KHz), 2(32KHz) or 3(sample rate converter) (RO).
	3	0	gstat	Generation status original/commercially pre-recorded data (0x1) or none (0x0) (RO).
	2	0	pre-emphasis	Pre-emphasis 50/15s (0x1) or none (0x0) (RO).
	1	0	copy	Copy permitted (0x1) or inhibited (0x0) (RO).
	0	0	audio	Data format is non-audio (0x1) or audio (0x0) (RO).
1. For AXI-Lite byte addresses, multiply by 4.

Using the ADV7511 Transmitter Library

The transmitter library is a collection of APIs that provide a consistent interface to ADV7511. The library is a software layer that sits between the application and the TX hardware. The library is intended to serve two purposes:

Provide the application with a set of APIs that can be used to configure HDMI TX hardware without the need for low-level register access. This makes the application portable across different revisions of the hardware and even across different hardware modules.
Provide basic services to aid the application in controlling the TX module, such as interrupt service routine, HDCP high-level control and status information.

The Demo project uses the ADV7511 Transmitter Library. The project is an example of how to:

Initialize the ADV7511 High-Definition Multimedia Interface (HDMI?) transmitter.
Check current AVR operating mode and depending on this result set the AV mute state.
Display an image and play a sound.

The project contains 2 components: the Demo project files and the ADV7511 Transmitter Library. All the components have to be downloaded from the links provided in the Downloads section.

Software Setup

The ADV7511 Transmitter Library Demo contains a folder called SDK_Workspace which stores the Xilinx SDK project files needed to build the no-OS software and also the .bit files with the HDL design that must be programmed into the FPGA. These are the steps that need to be followed to recreate the software project:

Copy the SDK_Workspace folder on your PC. Make sure that the path where it is stored does not contain any spaces.
Copy the library file to the SDK_Workspace/sw/lib folder.

Copy the library headers to the SDK_Workspace/sw/inc folder.

Copy the ADV7511 Transmitter Library Demo files to the SDK_Workspace/sw/src folder.

Open the Xilinx SDK. When the SDK starts it asks for a to provide a folder where to store the workspace. Any folder can be provided.
In the SDK select the File→Import menu option to import the software projects into the workspace.

In the Import window select the General→Existing Projects into Workspace option.

In the Import Projects window select the SDK_Workspace folder as root directory. After the root directory is chosen the projects that reside in that directory will appear in the Projects list. Press Finish to finalize the import process.

The Project Explorer window now shows the projects that exist in the workspace and the files for each project. The SDK should automatically build the projects and the Console window will display the result of the build. If the build is not done automatically select the Project→Build Automatically menu option.

Downloads

HDL Reference Designs:

FMCIMAGEONG

Hardware	Project	Carriers	Library Cores
AES-FMC-IMAGEON-G	imageon	zed	axi_clkgen
			axi_dmac
			axi_hdmi_rx
			axi_hdmi_tx
			axi_i2s_adi
			axi_spdif_rx
			axi_spdif_tx
			axi_sysid
			sysid_rom
			util_axis_fifo
			util_cdc

13 Feb 2015 18:57 · rejeesh kutty

ADV7511 Transmitter Library Demo Software

* ADV7511 Transmitter Library: https://www.analog.com/media/en/dsp-hardware-software/software-modules/ADV7511_API_Library.exe
* ADV7511 Transmitter Library Demo files: https://github.com/analogdevicesinc/no-OS/tree/adv7511_rework/projects/adv7511

Help & Support

The carriers (abbrevations can be found here) are commonly available FPGA evaluation boards.
The HDL user guide contains all the documentation, build instructions and register map tables.
The following quick links allows you to browse the github repository for a list of current branches, library components, and projects.
Questions? We can help with FPGA questions, Linux driver questions, No-OS Drivers questions.